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Timing Analysis in Digital Silicon Devices: Challenges and Techniques for Timing Closure in Modern Chips by Davide Sarta, VP of SoC Engineering, EnSilica, Bristol


IEEE Nanotechnology UK & Ireland Chapter and University of Bristol IEEE Student Branch are pleased to announce a joint industry talk – Timing Analysis in digital silicon devices: Challenges and techniques for timing closure in modern chips – at the University of Bristol.


  • 14:20-14:30 Registration
  • 14:30-15:50 EnSilica Talk
  • 15:50-16:00 Q&A


One of the main concerns of a team designing a silicon chip is timing. Achieving the required timing target may need many iterations and several months of architecture, design and implementation analysis and design. Besides functional verification, the timing closure is the major milestone which dictates when a chip can be released to manufacturing.

Starting from the basic concepts around static timing analysis, this presentation will describe the evolution of the field and, through real examples, the challenges that the silicon engineers, designing complex digital chips in the advanced process nodes, face today.

About the Speaker

Davide graduated in Electronic Engineering at the University of Catania, Italy, with a master’s in Control Systems and a second master’s in Low Power Silicon Design obtained at the Politecnico di Milano, Italy.

He has over 25 years of experience in the development of complex digital SoC, with many products taped out successfully in mass production, on process nodes down to 7nm, and different applications ranging from 5G, AI, Set Top Boxes, Cable gateway, and HPC. He is based in Bristol and currently manages the EnSilica SoC engineering organization based in Bristol, Oxford, Porto Alegre (Brazil) and Bangalore (India).

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