The presentation starts with an introduction to memory systems in computing devices such as computers, tablets or smartphones, following which an in depth analysis of standard memory systems for low power and high performance applications will be provided.
The interactions between the signalling clocking architecture and packaging technology of a memory interface as well as how these interactions determine the achievable data rates and power efficiency are discussed Signalling and clocking schemes for standard memories, including DDR 3 and DDR 4 (DDR 5 and mobile memories, such as LPDDR 3 and LPPDR 4 (LPDDR 5 are detailed and compared against each other.
The emerging 2 5 D/ 3 D memory systems such as HBM 1 2 2 E, and HMC 1 2 and beyond are also presented. Packaging options such as BGA, PoP and the emerging 2 5 D/ 3 D are also discussed. To analyse and compare different state of the art memory interfaces, the following metrics are used in the analysis cost, power efficiency, bandwidth, design complexity, signal and power integrity, thermal solution, and form factor.
The audience will gain an in depth understanding of high speed memory interfaces learn about the interactions between the signalling clocking architecture and packaging technology of a memory interface, and find out how those interactions determine the achievable data rates and power efficiency. The presentation will conclude by demonstrating how this knowledge can be used to analyse and compare different state of the art memory interfaces to help attendees implement or select a solution which best fits their specific application.
About the Speaker
Dr Wendem T. Beyene was born in Addis Ababa, Ethiopia. He received the B.S. and M.S. degrees in electrical engineering from Columbia University, New York, NY, USA, in 1988 and 1991, respectively, and the Ph.D. degree in electrical and computer engineering from the University of Illinois at Urbana Champaign, USA, in 1997. In the past, he was employed by IBM, Hewlett Packard, and Agilent Technologies. In 2000, he joined Rambus Inc., Los Altos, CA, USA, and was responsible for signal integrity of multi gigabit parallel and serial interfaces. During 2017 2020 he worked at Intel and was responsible for signal and power integrity analysis of high performance FPGA including fabric and high speed I/O subsystems as well as I/O modelling.
In 2020 he joined Facebook as an Analog & Mixed Signal Architect in Meta Reality Lab. Dr Beyene has authored or co-authored numerous refereed publications in various leading IEEE Transactions and conferences. These publications covered various disciplines including package and interconnect modelling , interface design and analysis as well as application of machine learning and optimization techniques to signal and power integrity of complex systems. He is currently a Senior Area Editor of Electrical Performance of Integrated Systems of IEEE Trans. On CPMT and is a Senior Member of Institute of Electrical and Electronic Engineers (IEEE). He also serves on several leading technical program committees, including EPEPS and DTMES.
This presentation is free to attend, and open to all, whether you are an IEEE member, EMC Society member, or not. Advance registration is not required, but it would aid in our planning if you can indicate if you plan to attend by registering using the button below.