ARITH 24 – 24th IEEE Symposium on Computer Arithmetic

Since 1969, the ARITH symposia have served as the flagship conference for presenting scientific work on the latest research in computer arithmetic. Authors are invited to submit papers describing recent advances on all aspects of computer arithmetic and its applications or implementations. This includes, but is not restricted to, the following topics:

• Foundations of number systems and arithmetic
• Arithmetic processor design and implementation
• Arithmetic algorithms and their analysis
• Floating-point units, algorithms, and numerical analysis
• Elementary and special function implementations
• Power-efficient or low-energy arithmetic units and processors
• Industrial implementation of arithmetic units and processors
• Test, validation, and formal verification techniques for arithmetic implementations
• Fault/error-tolerance in arithmetic implementations
• Arithmetic for FPGAs and reconfigurable logic
• Design automation for computer arithmetic implementations
• Computer arithmetic for security and cryptography
• Arithmetic to enhance accuracy or reliability (multiple-precision, interval arithmetic, …)
• Arithmetic challenges in HPC and exascale computing (accuracy, reproducibility, …)
• Arithmetic for specific application domains (big-data analytics, signal processing, computer graphics, multimedia, computer vision, finance, …)
• Computer arithmetic in emerging technologies
• Non-conventional computer arithmetic and applications

Early registration deadline is June 1st 2017.